Discussion:
armv7 pmap fix for Cortex A53 (and Cortex A7?)
(too old to reply)
Mark Kettenis
2016-07-31 18:03:58 UTC
Permalink
The ARMv7 ARM says in B3.9 that

The architecture guarantees that a translation table entry that
generates a Translation fault or an Access flag fault is not held in
the TLB. However a translation table entry that generates a Domain
fault or a Permission fault might be held in the TLB.

and that

Any translation table entry that does not generate a Translation or
Access flag fault and is not out of context might be allocated to an
enabled TLB at any time. The only translation table entries guaranteed
not to be held in the TLB are those that generate a Translation or
Access flag fault.

So the CPU might speculatively load TLB entries. The upshot from this
is that we always have to perform a TLB flush if we modify a valid
entry. So we can't rely on PV_BEEN_REFD() to decide whether we should
flush or not. The diff below fixes thi. The diff seems to fix the
pmap_fault_fixup() messages on a Cortex A53 system. It's very likely
that this will fix them on Cortex A7 as well.


Index: arch/arm/arm/pmap7.c
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/pmap7.c,v
retrieving revision 1.29
diff -u -p -r1.29 pmap7.c
--- arch/arm/arm/pmap7.c 29 Jul 2016 06:46:15 -0000 1.29
+++ arch/arm/arm/pmap7.c 31 Jul 2016 17:55:27 -0000
@@ -373,13 +373,7 @@ struct pv_entry {
* Macro to determine if a mapping might be resident in the
* instruction cache and/or TLB
*/
-#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
-
-/*
- * Macro to determine if a mapping might be resident in the
- * data cache and/or TLB
- */
-#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
+#define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) != 0)

/*
* Local prototypes
@@ -1034,11 +1028,12 @@ pmap_clearbit(struct vm_page *pg, u_int
*ptep = npte;
PTE_SYNC(ptep);
/* Flush the TLB entry if a current pmap. */
- if (PV_BEEN_EXECD(oflags))
- pmap_tlb_flushID_SE(pm, pv->pv_va);
- else
- if (PV_BEEN_REFD(oflags))
- pmap_tlb_flushD_SE(pm, pv->pv_va);
+ if (l2pte_valid(opte)) {
+ if (PV_BEEN_EXECD(oflags))
+ pmap_tlb_flushID_SE(pm, pv->pv_va);
+ else
+ pmap_tlb_flushD_SE(pm, pv->pv_va);
+ }
}

NPDEBUG(PDB_BITS,
@@ -1454,11 +1449,12 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
}
}

- if (PV_BEEN_EXECD(oflags))
- pmap_tlb_flushID_SE(pm, va);
- else
- if (PV_BEEN_REFD(oflags))
- pmap_tlb_flushD_SE(pm, va);
+ if (l2pte_valid(opte)) {
+ if (PV_BEEN_EXECD(oflags))
+ pmap_tlb_flushID_SE(pm, va);
+ else
+ pmap_tlb_flushD_SE(pm, va);
+ }
}

/*
@@ -1484,7 +1480,7 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
struct l2_bucket *l2b;
vaddr_t next_bucket;
pt_entry_t *ptep;
- u_int mappings, is_exec, is_refd;
+ u_int mappings, is_exec;

NPDEBUG(PDB_REMOVE, printf("pmap_remove: pmap=%p sva=%08lx eva=%08lx\n",
pm, sva, eva));
@@ -1525,7 +1521,6 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
pm->pm_stats.resident_count--;
pa = l2pte_pa(pte);
is_exec = 0;
- is_refd = l2pte_valid(pte);

/*
* Update flags. In a number of circumstances,
@@ -1538,7 +1533,6 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
pve = pmap_remove_pv(pg, pm, sva);
if (pve != NULL) {
is_exec = PV_BEEN_EXECD(pve->pv_flags);
- is_refd = PV_BEEN_REFD(pve->pv_flags);
pool_put(&pmap_pv_pool, pve);
}
}
@@ -1553,11 +1547,12 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd

*ptep = L2_TYPE_INV;
PTE_SYNC(ptep);
- if (is_exec)
- pmap_tlb_flushID_SE(pm, sva);
- else
- if (is_refd)
- pmap_tlb_flushD_SE(pm, sva);
+ if (l2pte_valid(pte)) {
+ if (is_exec)
+ pmap_tlb_flushID_SE(pm, sva);
+ else
+ pmap_tlb_flushD_SE(pm, sva);
+ }

sva += PAGE_SIZE;
ptep++;
@@ -1732,7 +1727,7 @@ void
pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
{
struct l2_bucket *l2b;
- pt_entry_t *ptep, pte;
+ pt_entry_t *ptep, pte, opte;
vaddr_t next_bucket;
u_int flags;
int flush;
@@ -1782,19 +1777,19 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
ptep = &l2b->l2b_kva[l2pte_index(sva)];

while (sva < next_bucket) {
- pte = *ptep;
+ opte = *ptep;
/* !!! not l2pte_valid */
/* XXX actually would only matter if really valid ??? */
- if (pte != 0 && l2pte_is_writeable(pte, pm)) {
+ if (opte != 0 && l2pte_is_writeable(opte, pm)) {
struct vm_page *pg;
u_int f;

- pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
+ pg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
if (pg != NULL)
pmap_clean_page(pg, FALSE);
- pte = (pte & ~L2_S_PROT_MASK) |
+ pte = (opte & ~L2_S_PROT_MASK) |
L2_S_PROT(pm == pmap_kernel() ? PTE_KERNEL : PTE_USER,
- pte & L2_V7_S_XN ? PROT_READ : PROT_READ | PROT_EXEC);
+ opte & L2_V7_S_XN ? PROT_READ : PROT_READ | PROT_EXEC);
*ptep = pte;
PTE_SYNC(ptep);

@@ -1802,15 +1797,16 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
f = pmap_modify_pv(pg, pm, sva,
PVF_WRITE, 0);
} else
- f = PVF_REF | PVF_EXEC;
+ f = PVF_EXEC;

if (flush >= 0) {
flush++;
- if (PV_BEEN_EXECD(f))
- cpu_tlb_flushID_SE(sva);
- else
- if (PV_BEEN_REFD(f))
- cpu_tlb_flushD_SE(sva);
+ if (l2pte_valid(opte)) {
+ if (PV_BEEN_EXECD(f))
+ cpu_tlb_flushID_SE(sva);
+ else
+ cpu_tlb_flushD_SE(sva);
+ }
} else
flags |= f;
}
@@ -1824,7 +1820,6 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
if (PV_BEEN_EXECD(flags))
pmap_tlb_flushID(pm);
else
- if (PV_BEEN_REFD(flags))
pmap_tlb_flushD(pm);
}
NPDEBUG(PDB_PROTECT, printf("\n"));
Juan Francisco Cantero Hurtado
2016-08-01 00:50:57 UTC
Permalink
The patch doesn't fix the bug on Cortex A7.

cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache



Scanning scsi 0:1...
reading /sun7i-a20-olinuxino-lime2.dtb
29895 bytes read in 8 ms (3.6 MiB/s)
Found EFI removable media binary efi/boot/bootarm.efi
reading efi/boot/bootarm.efi
65196 bytes read in 9 ms (6.9 MiB/s)
## Starting EFI application at 0x42000000 ...
Scanning disks on scsi...
Scanning disks on usb...
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 2 disks
Post by Mark Kettenis
OpenBSD/armv7 BOOTARM 0.1
boot>
booting sd0a:/bsd: 3504220+97840+476376 [64+464640+214774]=0x48a2b4

OpenBSD/armv7 booting ...
arg0 0x40000000 arg1 0x10bb arg2 0x48000000
Allocating page tables
freestart = 0x4078b000, free_pages = 260213 (0x0003f875)
IRQ stack: p0x407b9000 v0xc07b9000
ABT stack: p0x407ba000 v0xc07ba000
UND stack: p0x407bb000 v0xc07bb000
SVC stack: p0x407bc000 v0xc07bc000
Creating L1 page table at 0x4078c000
Mapping kernel
Constructing L2 page tables
undefined page pmap [ using 679852 bytes of bsd ELF symbol table ]
board type: 4283
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights
reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved.
http://www.OpenBSD.org

OpenBSD 6.0-current (GENERIC) #1: Mon Aug 1 02:40:31 CEST 2016
***@lime2.juanfra:/usr/src/sys/arch/armv7/compile/GENERIC
real mem = 1073741824 (1024MB)
avail mem = 1044840448 (996MB)
mainbus0 at root: Olimex A20-OLinuXino-LIME2
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch
prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back
D-cache
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
agtimer0 at cortex0: tick rate 24000 KHz
sunxi0 at mainbus0
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxidog0 at sunxi0
sxirtc0 at sunxi0
ahci0 at sunxi0 AHCI 1.1
ahci0: port 0: 1.5Gb/s
scsibus0 at ahci0: 32 targets
sd0 at scsibus0 targ 0 lun 0: <ATA, HTS721010G9SA00, MCZI>
SCSI3 0/direct fixed t10.ATA_HTS721010G9SA00_MPCZN7Y0J9XTDL
sd0: 95396MB, 512 bytes/sector, 195371568 sectors
ehci0 at sunxi0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
ehci1 at sunxi0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
gpio0 at sxipio0: 18 pins
gpio1 at sxipio0: 24 pins
gpio2 at sxipio0: 25 pins
gpio3 at sxipio0: 28 pins
gpio4 at sxipio0: 12 pins
gpio5 at sxipio0: 6 pins
gpio6 at sxipio0: 12 pins
gpio7 at sxipio0: 28 pins
gpio8 at sxipio0: 22 pins
simplebus0 at mainbus0: "soc"
sxiuart0 at simplebus0: console
run0 at uhub1 port 1 configuration 1 interface 0 "Ralink
802.11 n WLAN" rev 2.00/1.01 addr 2
run0: MAC/BBP RT5390 (rev 0x0502), RF RT5370 (MIMO 1T1R),
address 7c:dd:90:02:47:50
vscsi0 at root
scsibus1 at vscsi0: 256 targets
softraid0 at root
scsibus2 at softraid0: 256 targets
boot device: sd0
root on sd0a (5e1e16eae3186591.a) swap on sd0b dump on sd0b
Automatic boot in progress: starting file system checks.
/dev/sd0a (5e1e16eae3186591.a): file system is clean; not
checking
setting tty flags
pf enabled
pmap_fault_fixup: va 00008000 ftype 5 u pte 7efaf02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7efaf02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7efaf02e
Post by Mark Kettenis
The ARMv7 ARM says in B3.9 that
The architecture guarantees that a translation table entry that
generates a Translation fault or an Access flag fault is not held in
the TLB. However a translation table entry that generates a Domain
fault or a Permission fault might be held in the TLB.
and that
Any translation table entry that does not generate a Translation or
Access flag fault and is not out of context might be allocated to an
enabled TLB at any time. The only translation table entries guaranteed
not to be held in the TLB are those that generate a Translation or
Access flag fault.
So the CPU might speculatively load TLB entries. The upshot from this
is that we always have to perform a TLB flush if we modify a valid
entry. So we can't rely on PV_BEEN_REFD() to decide whether we should
flush or not. The diff below fixes thi. The diff seems to fix the
pmap_fault_fixup() messages on a Cortex A53 system. It's very likely
that this will fix them on Cortex A7 as well.
Index: arch/arm/arm/pmap7.c
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/pmap7.c,v
retrieving revision 1.29
diff -u -p -r1.29 pmap7.c
--- arch/arm/arm/pmap7.c 29 Jul 2016 06:46:15 -0000 1.29
+++ arch/arm/arm/pmap7.c 31 Jul 2016 17:55:27 -0000
@@ -373,13 +373,7 @@ struct pv_entry {
* Macro to determine if a mapping might be resident in the
* instruction cache and/or TLB
*/
-#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
-
-/*
- * Macro to determine if a mapping might be resident in the
- * data cache and/or TLB
- */
-#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
+#define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) != 0)
/*
* Local prototypes
@@ -1034,11 +1028,12 @@ pmap_clearbit(struct vm_page *pg, u_int
*ptep = npte;
PTE_SYNC(ptep);
/* Flush the TLB entry if a current pmap. */
- if (PV_BEEN_EXECD(oflags))
- pmap_tlb_flushID_SE(pm, pv->pv_va);
- else
- if (PV_BEEN_REFD(oflags))
- pmap_tlb_flushD_SE(pm, pv->pv_va);
+ if (l2pte_valid(opte)) {
+ if (PV_BEEN_EXECD(oflags))
+ pmap_tlb_flushID_SE(pm, pv->pv_va);
+ else
+ pmap_tlb_flushD_SE(pm, pv->pv_va);
+ }
}
NPDEBUG(PDB_BITS,
@@ -1454,11 +1449,12 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
}
}
- if (PV_BEEN_EXECD(oflags))
- pmap_tlb_flushID_SE(pm, va);
- else
- if (PV_BEEN_REFD(oflags))
- pmap_tlb_flushD_SE(pm, va);
+ if (l2pte_valid(opte)) {
+ if (PV_BEEN_EXECD(oflags))
+ pmap_tlb_flushID_SE(pm, va);
+ else
+ pmap_tlb_flushD_SE(pm, va);
+ }
}
/*
@@ -1484,7 +1480,7 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
struct l2_bucket *l2b;
vaddr_t next_bucket;
pt_entry_t *ptep;
- u_int mappings, is_exec, is_refd;
+ u_int mappings, is_exec;
NPDEBUG(PDB_REMOVE, printf("pmap_remove: pmap=%p sva=%08lx eva=%08lx\n",
pm, sva, eva));
@@ -1525,7 +1521,6 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
pm->pm_stats.resident_count--;
pa = l2pte_pa(pte);
is_exec = 0;
- is_refd = l2pte_valid(pte);
/*
* Update flags. In a number of circumstances,
@@ -1538,7 +1533,6 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
pve = pmap_remove_pv(pg, pm, sva);
if (pve != NULL) {
is_exec = PV_BEEN_EXECD(pve->pv_flags);
- is_refd = PV_BEEN_REFD(pve->pv_flags);
pool_put(&pmap_pv_pool, pve);
}
}
@@ -1553,11 +1547,12 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
*ptep = L2_TYPE_INV;
PTE_SYNC(ptep);
- if (is_exec)
- pmap_tlb_flushID_SE(pm, sva);
- else
- if (is_refd)
- pmap_tlb_flushD_SE(pm, sva);
+ if (l2pte_valid(pte)) {
+ if (is_exec)
+ pmap_tlb_flushID_SE(pm, sva);
+ else
+ pmap_tlb_flushD_SE(pm, sva);
+ }
sva += PAGE_SIZE;
ptep++;
@@ -1732,7 +1727,7 @@ void
pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
{
struct l2_bucket *l2b;
- pt_entry_t *ptep, pte;
+ pt_entry_t *ptep, pte, opte;
vaddr_t next_bucket;
u_int flags;
int flush;
@@ -1782,19 +1777,19 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
ptep = &l2b->l2b_kva[l2pte_index(sva)];
while (sva < next_bucket) {
- pte = *ptep;
+ opte = *ptep;
/* !!! not l2pte_valid */
/* XXX actually would only matter if really valid ??? */
- if (pte != 0 && l2pte_is_writeable(pte, pm)) {
+ if (opte != 0 && l2pte_is_writeable(opte, pm)) {
struct vm_page *pg;
u_int f;
- pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
+ pg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
if (pg != NULL)
pmap_clean_page(pg, FALSE);
- pte = (pte & ~L2_S_PROT_MASK) |
+ pte = (opte & ~L2_S_PROT_MASK) |
L2_S_PROT(pm == pmap_kernel() ? PTE_KERNEL : PTE_USER,
- pte & L2_V7_S_XN ? PROT_READ : PROT_READ | PROT_EXEC);
+ opte & L2_V7_S_XN ? PROT_READ : PROT_READ | PROT_EXEC);
*ptep = pte;
PTE_SYNC(ptep);
@@ -1802,15 +1797,16 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
f = pmap_modify_pv(pg, pm, sva,
PVF_WRITE, 0);
} else
- f = PVF_REF | PVF_EXEC;
+ f = PVF_EXEC;
if (flush >= 0) {
flush++;
- if (PV_BEEN_EXECD(f))
- cpu_tlb_flushID_SE(sva);
- else
- if (PV_BEEN_REFD(f))
- cpu_tlb_flushD_SE(sva);
+ if (l2pte_valid(opte)) {
+ if (PV_BEEN_EXECD(f))
+ cpu_tlb_flushID_SE(sva);
+ else
+ cpu_tlb_flushD_SE(sva);
+ }
} else
flags |= f;
}
@@ -1824,7 +1820,6 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
if (PV_BEEN_EXECD(flags))
pmap_tlb_flushID(pm);
else
- if (PV_BEEN_REFD(flags))
pmap_tlb_flushD(pm);
}
NPDEBUG(PDB_PROTECT, printf("\n"));
--
Juan Francisco Cantero Hurtado http://juanfra.info
Daniel Bolgheroni
2016-08-01 02:02:07 UTC
Permalink
Post by Mark Kettenis
So the CPU might speculatively load TLB entries. The upshot from this
is that we always have to perform a TLB flush if we modify a valid
entry. So we can't rely on PV_BEEN_REFD() to decide whether we should
flush or not. The diff below fixes thi. The diff seems to fix the
pmap_fault_fixup() messages on a Cortex A53 system. It's very likely
that this will fix them on Cortex A7 as well.
Hi Mark,

rebuilt RAMDISK and bsd.rd with the latest commits and tested on a Cubieboard 2
with Cortex-A7.

Thank you.

--

U-Boot SPL 2016.05 (Jul 02 2016 - 03:01:58)
DRAM: 1024 MiB
CPU: 912000000Hz, AXI/AHB/APB: 3/2/2
Trying to boot from MMC1


U-Boot 2016.05 (Jul 02 2016 - 03:01:58 -0600) Allwinner Technology

CPU: Allwinner A20 (SUN7I)
Model: Cubietech Cubieboard2
I2C: ready
DRAM: 1 GiB
MMC: SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
SCSI: SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net: eth0: ***@01c50000
starting USB...
USB0: USB EHCI 1.00
USB1: USB OHCI 1.0
USB2: USB EHCI 1.00
USB3: USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
reading /sun7i-a20-cubieboard2.dtb
29537 bytes read in 29 ms (994.1 KiB/s)
Found EFI removable media binary efi/boot/bootarm.efi
reading efi/boot/bootarm.efi
65276 bytes read in 41 ms (1.5 MiB/s)
## Starting EFI application at 0x42000000 ...
Scanning disks on scsi...
Scanning disks on usb...
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 2 disks
Post by Mark Kettenis
OpenBSD/armv7 BOOTARM 0.1
boot> boot bsd.rd
cannot open sd0a:/etc/random.seed: No such file or directory
booting sd0a:bsd.rd: 2093312+7928836+428484 [64+297264+142723]=0xa63e30

OpenBSD/armv7 booting ...
arg0 0x40000000 arg1 0x10bb arg2 0x48000000
Allocating page tables
freestart = 0x40d64000, free_pages = 258716 (0x0003f29c)
IRQ stack: p0x40d92000 v0xc0d92000
ABT stack: p0x40d93000 v0xc0d93000
UND stack: p0x40d94000 v0xc0d94000
SVC stack: p0x40d95000 v0xc0d95000
Creating L1 page table at 0x40d64000
Mapping kernel
Constructing L2 page tables
undefined page pmap board type: 4283
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved. http://www.OpenBSD.org

OpenBSD 6.0-current (RAMDISK) #0: Sun Jul 31 22:39:32 BRT 2016
***@wbs.my.domain:/usr/src/sys/arch/armv7/compile/RAMDISK
real mem = 1073741824 (1024MB)
avail mem = 1038827520 (990MB)
mainbus0 at root: Cubietech Cubieboard2
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
agtimer0 at cortex0: tick rate 24000 KHz
sunxi0 at mainbus0
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxidog0 at sunxi0
sxirtc0 at sunxi0
ahci0 at sunxi0 AHCI 1.1
scsibus0 at ahci0: 32 targets
ehci0 at sunxi0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
ehci1 at sunxi0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
gpio0 at sxipio0: 18 pins
gpio1 at sxipio0: 24 pins
gpio2 at sxipio0: 25 pins
gpio3 at sxipio0: 28 pins
gpio4 at sxipio0: 12 pins
gpio5 at sxipio0: 6 pins
gpio6 at sxipio0: 12 pins
gpio7 at sxipio0: 28 pins
gpio8 at sxipio0: 22 pins
simplebus0 at mainbus0: "soc"
sxiuart0 at simplebus0: console
boot device: lookup 'sd0a:/bsd' failed.
root on rd0a swap on rd0b dump on rd0b
WARNING: clock lost 17013 days
WARNING: CHECK AND RESET THE DATE!
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff2b02e

uvm_fault(0xca49c130, 10000, 2, 0) -> d
Fatal kernel mode data abort: 'Translation Fault (P)'
trapframe: 0xcc3b8dd8
DFSR=00002807, DFAR=00010000, spsr=80000113
r0 =00010000, r1 =00000fff, r2 =00000000, r3 =0000001f
r4 =cc3b9000, r5 =ca49b838, r6 =00000005, r7 =c0cf5a3c
r8 =00000000, r9 =c0cf61f4, r10=c0cf5a3c, r11=cc3b8e70
r12=00000020, ssp=cc3b8e28, slr=c041651c, pc =c040ee4c

panic: Fatal abort
syncing disks... done
rebooting...
--
db
Daniel Bolgheroni
2016-08-02 01:19:17 UTC
Permalink
Post by Mark Kettenis
So the CPU might speculatively load TLB entries. The upshot from this
is that we always have to perform a TLB flush if we modify a valid
entry. So we can't rely on PV_BEEN_REFD() to decide whether we should
flush or not. The diff below fixes thi. The diff seems to fix the
pmap_fault_fixup() messages on a Cortex A53 system. It's very likely
that this will fix them on Cortex A7 as well.
Tested on Cortex-A8 and it seems ok.

--

U-Boot SPL 2016.07 (Jul 12 2016 - 14:45:59)
Trying to boot from MMC1
MMC partition switch failed
*** Warning - MMC partition switch failed, using default environment

reading u-boot.img
reading u-boot.img


U-Boot 2016.07 (Jul 12 2016 - 14:45:59 +1000)

Watchdog enabled
I2C: ready
DRAM: 512 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Press SPACE to abort autoboot in 2 seconds
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
reading boot.scr
** Unable to read file boot.scr **
reading uEnv.txt
** Unable to read file uEnv.txt **
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
reading /am335x-boneblack.dtb
32577 bytes read in 9 ms (3.5 MiB/s)
Found EFI removable media binary efi/boot/bootarm.efi
reading efi/boot/bootarm.efi
65276 bytes read in 14 ms (4.4 MiB/s)
## Starting EFI application at 0x82000000 ...
Scanning disks on usb...
Scanning disks on mmc...
MMC Device 2 not found
MMC Device 3 not found
Found 6 disks
Post by Mark Kettenis
OpenBSD/armv7 BOOTARM 0.1
boot> boot tbsd
booting sd0a:tbsd: 3674688+100668+479244 [64+490880+230122]=0x4c5b68

OpenBSD/armv7 booting ...
arg0 0x80000000 arg1 0xe05 arg2 0x88000000
Allocating page tables
freestart = 0x807c6000, free_pages = 129082 (0x0001f83a)
IRQ stack: p0x807f4000 v0xc07f4000
ABT stack: p0x807f5000 v0xc07f5000
UND stack: p0x807f6000 v0xc07f6000
SVC stack: p0x807f7000 v0xc07f7000
Creating L1 page table at 0x807c8000
Mapping kernel
Constructing L2 page tables
undefined page pmap [ using 721440 bytes of bsd ELF symbol table ]
board type: 3589
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved. http://www.OpenBSD.org

OpenBSD 6.0-current (GENERIC) #0: Mon Aug 1 18:57:26 BRT 2016
***@wbs.my.domain:/usr/src/sys/arch/armv7/compile/GENERIC
real mem = 536870912 (512MB)
avail mem = 518017024 (494MB)
mainbus0 at root: TI AM335x BeagleBone Black
cpu0 at mainbus0: ARM Cortex A8 R3 rev 2 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(64b/l,4way) I-cache, 32KB(64b/l,4way) wr-back D-cache
omap0 at mainbus0
prcm0 at omap0 rev 0.2
sitaracm0 at omap0: control module, rev 1.0
intc0 at omap0 rev 5.0
edma0 at omap0 rev 0.0
dmtimer0 at omap0 rev 3.1
dmtimer1 at omap0 rev 3.1
omgpio0 at omap0: rev 0.1
gpio0 at omgpio0: 32 pins
omgpio1 at omap0: rev 0.1
gpio1 at omgpio1: 32 pins
omgpio2 at omap0: rev 0.1
gpio2 at omgpio2: 32 pins
omgpio3 at omap0: rev 0.1
gpio3 at omgpio3: 32 pins
simplebus0 at mainbus0: "ocp"
simplebus1 at simplebus0: "l4_wkup"
simplebus2 at simplebus1: "scm"
com0 at simplebus0: ti16750, 64 byte fifo
com0: console
tiiic0 at simplebus0 rev 0.11
iic0 at tiiic0
"ti,tps65217" at iic0 addr 0x24 not configured
"at,24c256" at iic0 addr 0x50 not configured
"nxp,tda998x" at iic0 addr 0x70 not configured
tiiic1 at simplebus0 rev 0.11
iic1 at tiiic1
"at,24c256" at iic1 addr 0x54 not configured
"at,24c256" at iic1 addr 0x55 not configured
"at,24c256" at iic1 addr 0x56 not configured
"at,24c256" at iic1 addr 0x57 not configured
ommmc0 at simplebus0
sdmmc0 at ommmc0: 1-bit, mmc high-speed
ommmc1 at simplebus0
sdmmc1 at ommmc1: 1-bit, mmc high-speed
omdog0 at simplebus0 rev 0.1
cpsw0 at simplebus0: version 1.12 (0), address 1c:ba:8c:97:a7:03
ukphy0 at cpsw0 phy 0: Generic IEEE 802.3u media interface, rev. 1: OUI 0x0001f0, model 0x000f
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SS16G, 0080> SCSI2 0/direct fixed
sd0: 15193MB, 512 bytes/sector, 31116288 sectors
scsibus1 at sdmmc1: 2 targets, initiator 0
sd1 at scsibus1 targ 1 lun 0: <SD/MMC, MMC02G, 0000> SCSI2 0/direct fixed
sd1: 1832MB, 512 bytes/sector, 3751936 sectors
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
boot device: sd0
root on sd0a (fe311afb0f7c1b3f.a) swap on sd0b dump on sd0b
WARNING: CHECK AND RESET THE DATE!
Automatic boot in progress: starting file system checks.
/dev/sd0a (fe311afb0f7c1b3f.a): file system is clean; not checking
/dev/sd0j (fe311afb0f7c1b3f.j): file system is clean; not checking
/dev/sd0d (fe311afb0f7c1b3f.d): file system is clean; not checking
/dev/sd0f (fe311afb0f7c1b3f.f): file system is clean; not checking
/dev/sd0g (fe311afb0f7c1b3f.g): file system is clean; not checking
/dev/sd0h (fe311afb0f7c1b3f.h): file system is clean; not checking
/dev/sd0e (fe311afb0f7c1b3f.e): file system is clean; not checking
setting tty flags
pf enabled
starting network
reordering libraries: done.
starting early daemons: syslogd pflogd ntpd.
starting RPC daemons:.
savecore: no core dump
checking quotas: done.
clearing /tmp
kern.securelevel: 0 -> 1
creating runtime link editor directory cache.
preserving editor files.
starting network daemons: sshd smtpd sndiod.
starting local daemons: cron.
Wed Jul 27 02:18:15 BRT 2016

OpenBSD/armv7 (bbb.my.domain) (console)

login:

--
db
Daniel Bolgheroni
2016-08-02 01:21:08 UTC
Permalink
Post by Daniel Bolgheroni
Post by Mark Kettenis
So the CPU might speculatively load TLB entries. The upshot from this
is that we always have to perform a TLB flush if we modify a valid
entry. So we can't rely on PV_BEEN_REFD() to decide whether we should
flush or not. The diff below fixes thi. The diff seems to fix the
pmap_fault_fixup() messages on a Cortex A53 system. It's very likely
that this will fix them on Cortex A7 as well.
Tested on Cortex-A8 and it seems ok.
My bad. This is related to the unified TLBs diff.

--
db

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